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May 1997
ML65T541* 3.3V High Speed Octal Buffer/Line Driver
GENERAL DESCRIPTION
The ML65T541 is a non-inverting octal buffer/line driver. The high operating frequency (66MHz driving a 50pF load) and low propagation delay (2ns) make it ideal for very high speed applications such as processor bus buffering cache/main memory control. The ML65T541 uses a unique analog implementation to eliminate the delays inherent in traditional digital designs. Schottky clamps reduce undershoot and overshoot, and special output driver circuits limit ground bounce. The ML65T541 conforms to the pinout and functionality of the industry standard FCT541 and is intended for applications where propagation delay is critical to the system design.
FEATURES
s Low propagation delay -- 2.0ns s Fast 8-bit buffer/line driver with three-state capability on the output s Schottky diode clamps on all inputs to handle undershoot and overshoot s Onboard schottky diodes minimize noise s Ground bounce controlled outputs s Industry standard FCT541 type pinout s Applications include high speed cache memory, main memory, processor bus buffering, and graphics cards
BLOCK DIAGRAM
*Some Packages Are Obsolete
VCC 20 VCC OE1 1 OE2 19
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
10 GND
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
*Some packages are obsolete
ML65T541
PIN CONFIGURATION
20-Pin QSOP
1G A0 YB0 A1 YB1 A2 YB2 A3 YB3 GND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
VCC 2G YA0 B0 YA1 B1 YA2 B2 YA3 B3
TOP VIEW
PIN DESCRIPTION
NAME Ai Bi OE1 & OE2 GND VCC I/O I O I I I DESCRIPTION Data Bus A Data Bus B Output Enable Signal Ground 3.3V supply
FUNCTION TABLE
OE1/OE2 H L L
L H X Z = Logic Low = Logic High = Don't Care = High Impedance
A X L H
B Z L H
ABSOLUTE MAXIMUM RATINGS
VCC ............................................................................... -0.3V to 7V DC Input voltage ................................ -0.3 to VCC + 0.3V AC Input voltage (< 20ns) ........................................ -3.0V DC Output voltage ............................. -0.3 to VCC + 0.3V Output sink current (per pin) ................................ 120mA Storage temperature ................................ -65C to 150C Junction temperature .............................................. 150C Thermal Impedance (JA) SOIC ............................................................... 96C/W QSOP ............................................................ 100C/W
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ML65T541
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
Unless otherwise stated, these specifications apply for: VCC = 3.3V 10%, TA = 0C to 70C (Note 1)
CONDITIONS MIN TYP MAX UNITS
AC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = 500) tPLH, tPHL tOE tOD CIN Propagation delay Output enable time OE1, OE2 to Bi Output disable time OE1, OE2 to Bi Input capacitance Ai to Bi (Note 2) 1.4 10 15 8 2.0 20 20 ns ns ns pF
DC ELECTRICAL CHARACTERISTICS (CLOAD = 50pF, RLOAD = ) VIH VIL IIH IIL IHI-Z IOS VIC VOH VOL ICC
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
Input high voltage Input low voltage Input high current Input low current
Logic HIGH (Note 3) Logic LOW (Note 3) Per pin, VIN = 3V Per pin, VIN = 0
2.0 0.8 0.2 0.3 0.8 0.8 5 -60 -0.7 2.4 0.6 55 80 -225 -1.2
V V mA mA A mA V V V mA
Three-state output current 0 < VIN < VCC Short circuit current Input clamp voltage Output high voltage Output low voltage Quiescent Power Supply Current VO = GND (Note 4) IIN = 18mA IOH = 100A (Note 5) IOL = 5mA (Notes 5,6) Freq = 0Hz, VIN = 0V, outputs open
Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. One line switching, see Figure 3, tPLH, tPHL versus CL. Inputs should be driven to within 0.3V of the rail. Although the inputs are TTL compatible, at the minimum logic high voltage, the circuit will draw current due to the buffer action ( 20mA per channel). Not more than one output should be shorted for more than a second. See Figure 2 for IOH versus VOH and IOL versus VOL data. The output can source or sink more than 100 mA when switching. IOL is only significant as a DC specification.
tR, tF 4ns, f = 66MHz 3V INPUT 0V 3V OUTPUT 0V 1.5V 1.5V tPLH 1.5V 1.5V tPHL
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ML65T541
Figure 1. Typical Switching Waveform, Four Outputs Switching into 50pF Loads.
140 120 IOH (mA) 20 0 -20 -40 -60 -80 -100 -120
IOL (mA)
100 80 60 40 20 0
0.0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
1
2 VOH (V)
3
VOL (V)
Figure 2a. Typical VOL Versus IOL for One Buffer Output.
3.0
250
Figure 2b. Typical VOH Versus IOH for One Buffer Output.
2.5
200
150pF
100pF
75pF
ICC (mA)
2.0
tPD (ns)
150
50pF
1.5
100
1.0
50
30pF
0.5
0 10
0.0 30 50 75 LOAD CAPACITANCE (pF) 100 150
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
Figure 3. Propagation Delay (tPLH, tPHL) Versus Load Capacitance, One Output Switching At 66MHz.
Figure 4. ICC Versus Frequency for Various Load Capacitances, Four Outputs Switching.
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ML65T541
FUNCTIONAL DESCRIPTION
The ML65T541 is a very high speed non-inverting buffer/ line driver with three-state outputs which is ideally suited for bus-oriented applications. It provides a low propagation delay by using an analog design approach (a high speed unity gain buffer), as compared to conventional digital approaches. The ML65T541 follows the pinout and functionality of the industry standard FCT541 series of buffers/line drivers and is intended to replace them in designs where the propagation delay is a critical part of the system design considerations. The ML65T541 is capable of driving load capacitances several times larger than its input capacitance. It is configured so that the Ai inputs go to the Bi outputs when enabled by OE1/OE2 These unity gain analog buffers achieve low propagation delays by having the output follow the input with a small offset. When the output reaches one VBE off the rail, the PMOS pull-up is activated to drive the output the rest of the way. All inputs and outputs have Schottky clamp diodes to handle undershoot or overshoot noise suppression in unterminated applications. All outputs have ground bounce suppression (typically < 400mV), high drive output capability with almost immediate response to the input signal, and low output skew. The IOL current drive capability of a buffer/line driver is often interpreted as a measure of its ability to sink current in a dynamic sense. This may be true for CMOS buffer/ line drivers, but it is not true for the ML65T541. This is because their sink and source current capability depends on the voltage difference between the output and the input. The ML65T541 can sink or source more than 100mA to a load when the load is switching due to the fact that during the transition, the difference between the input and output is large. IOL is only significant as a DC specification, and is 5mA.
ARCHITECTURAL DESCRIPTION
Until now, buffer/line drivers have been implemented in CMOS logic and made to be TTL compatible by sizing the input devices appropriately. In order to buffer large capacitances with CMOS logic, it is necessary to cascade an even number of inverters, each successive inverter larger than the preceding, eventually leading to an inverter that will drive the required load capacitance at the required frequency. Each inverter stage represents an additional delay in the gating process because in order for a single gate to switch, the input must slew more than half of the supply voltage. The best of these CMOS buffers has managed to drive a 50pF load capacitance with a delay of 3.2ns. Micro Linear has produced a dual quad buffer/line driver with a delay of less than 2ns by using a unique circuit architecture that does not require cascaded logic gates. The ML65T541 uses a feedback technique to produce an output that follows the input. If the output voltage is not close to the input, then the feedback circuitry will source or sink enough current to the load capacitance to correct the discrepancy. The basic architecture of the ML65T541 is shown in Figure 5. It is implemented on a 1.5m BiCMOS process.
VCC
R8
Q1
Q2
M1
INV
R3 R1 IN Q4
R4 R2
R7 OUT Q6
Q3
Q5
Q7
R5
R6
GND
Figure 5. One buffer cell of the ML65T541
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ML65T541
However, in this particular circuit, all of the active devices are NPNs -- the fastest devices available in the process. In this circuit, there are two paths to the output. One path sources current to the load capacitance when the signal is asserted, and the other path sinks current from the output when the signal is negated. The assertion path is the emitter follower path consisting of the level shift transistor Q1, the output transistor Q2, the pull-up helper M1 (static RON 200), and the bias resistor R8. It sources current to the output through the resistor R7 which is bypassed by another NPN (not shown) during fast input transients, and M1 pull-up drives the output toward the rail once the output reaches one VBE within the rail. The negation path is a current differencing op amp connected in a follower configuration. The active components in this amplifier are transistors Q3-Q7. R3- R6 are bias resistors, and R1 and R2 are the feedback resistors. The key to understanding the operation of the current differencing op amp is to know that the current in transistors Q3 and Q5 are the same at all times and that the voltages at the bases of Q4 and Q6 are roughly the same. If the output is higher than the input, then an error current will flow through R2. This error current will flow into the base of Q6 and be multiplied by squared to the collector of Q7, closing the loop. The larger the discrepancy between the output and input, the larger the feedback current, and the harder Q7 sinks current from the load capacitor. A number of MOSFETs are not shown in Figure 5. These MOSFETs are used to three-state dormant buffers. For instance, the feedback resistors R1 and R2 were implemented as resistive transmission gates to ensure that disabled buffers do not load the lines they are connected to. Similarly, there is a PMOS in series with R8 that is normally on but shuts off for disable. Other MOSFETs have been included to ensure that disabled buffers consume no power.
APPLICATIONS
There are a wide variety of needs for an extremely fast buffers in high speed processor system designs like Pentium, PowerPC, Mips, Sparc, Alpha and other RISC processors. These applications are either in the cache memory area or the main memory (DRAM) area. In addition, fast buffers find applications in high speed graphics and multimedia applications. The high capacitive loading due to multiplexed address lines on the system bus demand external buffers to take up the excess drive current. The needed current to skew the transitions between rise and fall times must be done without adding excessive propagation delay. The ML65T541 is equipped with Schottky diodes to clean up ringing from overshoot and undershoot caused by reflections in unterminated board traces.
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ML65T541
PHYSICAL DIMENSIONS inches (millimeters)
Package: S20 (Obsolete) 20-Pin SOIC
0.498 - 0.512 (12.65 - 13.00) 20
0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID
1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0 - 8
0.090 - 0.094 (2.28 - 2.39)
0.012 - 0.020 (0.30 - 0.51)
SEATING PLANE
0.005 - 0.013 (0.13 - 0.33)
0.022 - 0.042 (0.56 - 1.07)
0.007 - 0.015 (0.18 - 0.38)
Package: K20 20-Pin QSOP
0.338 - 0.348 (8.58 - 8.84) 20
PIN 1 ID
0.150 - 0.160 (3.81 - 4.06)
0.228 - 0.244 (5.79 - 6.20)
0.050 - 0.055 (1.27 - 1.40) (4 PLACES)
1 0.025 BSC (0.63 BSC) 0.060 - 0.068 (1.52 - 1.73) 0 - 8
0.055 - 0.061 (1.40 - 1.55)
0.008 - 0.012 (0.20 - 0.31) SEATING PLANE
0.004 - 0.010 (0.10 - 0.26)
0.015 - 0.035 (0.38 - 0.89)
0.006 - 0.010 (0.15 - 0.26)
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ML65T541
ORDERING INFORMATION
PART NUMBER ML65T541CK ML65T541CS SPEED 2.0ns 2.0ns TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 20-Pin QSOP (K20) 20-Pin SOIC (S20) (Obsolete)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
DS65T541-01
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